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Search - AES for FPGA

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[Crack Hack] 2005533243332

Description: AES加密软件，用于加密当前文本框中的内容。使用的是美国国家标准（也被ISO所采纳）最新加密算法AES。-AES encryption software, encryption for the current contents of the text box. The use of the American National Standards (also adopted by the ISO) the latest encryption algorithm AES.
Platform: | Size: 32768 | Author: 高志强 | Hits:

[Crack Hack] aes_encryption

Description: aes加密算法的VHDL代码实现，在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Platform: | Size: 6144 | Author: stym_001 | Hits:

[Crack Hack] Algorithms

Description: 密码算法AES,DES,IDEA,MD5等的基本理论和硬件加速方案，对算法进行fpga硬件加速的优点等-Cryptographic algorithm AES, DES, IDEA, MD5, etc. The basic theory and hardware acceleration program, the algorithm of the advantages of FPGA hardware acceleration, etc.
Platform: | Size: 1816576 | Author: 胡昊 | Hits:

[Software Engineering] AES

Description: 基于fpga的AES高速实现，介绍了算法实现的过程，仿真结果。-FPGA-based high-speed realization of the AES, introduced the process of algorithm, the simulation results.
Platform: | Size: 1415168 | Author: 王旺 | Hits:

[Crack Hack] khalil2006_true_random_number_generator

Description: a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are required to generate public/private key pairs for asymmetric algorithm such as RSA and symmetric algorithm such as AES.
Platform: | Size: 418816 | Author: Hassan Abdelaziz | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[Software Engineering] platforms

Description: A Pipelined Implementation of AES for Altera FPGA platforms.doc
Platform: | Size: 86016 | Author: Mohammad | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[VHDL-FPGA-Verilog] aescore

Description: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Platform: | Size: 195584 | Author: 李华 | Hits:

[Embeded-SCM Develop] FPGA

Description: 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code description of the design process, operation circuit modeling, algorithm programming
Platform: | Size: 3852288 | Author: betty | Hits:

[VHDL-FPGA-Verilog] AES-algorithm-design

Description: 基于FPGA的AES算法芯片设计实现,文中具体给出了测试的运行时间等数据-AES algorithm for FPGA-based chip design to achieve
Platform: | Size: 121856 | Author: menshuang | Hits:

[Crack Hack] AES-implementation-based-on-FPGA

Description: 一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference
Platform: | Size: 356352 | Author: menshuang | Hits:

[VHDL-FPGA-Verilog] 1

Description: 一种基于FPGA的AES算法的低功耗实现,对于AES低功耗设计有帮助作用-FPGA-based AES algorithm to achieve low power consumption, low-power design for the AES helpful
Platform: | Size: 156672 | Author: menshuang | Hits:

[VHDL-FPGA-Verilog] 09912007AEScoremodules

Description: aes description architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
Platform: | Size: 6144 | Author: tarang | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
Platform: | Size: 133120 | Author: weipingzhang | Hits:

[VHDL-FPGA-Verilog] FPGA--AES-algorithm

Description: 本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方 案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback 两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the limited domain knowledge and simple computing the program an FPGA high-speed AES algorithm, the encryption module of the program supports three key lengths for AES standard: 128,192,256, supports three operating modes ECB, CBC, CTR, which is to support two modes of feedback and non-feedback. Finally, the performance of the design
Platform: | Size: 240640 | Author: 李仁杰 | Hits:

[VHDL-FPGA-Verilog] dec_aes

Description: decription aes vhdl code for fpga
Platform: | Size: 12288 | Author: dani.hassoun | Hits:

[File Format] AES-FPGA

Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
Platform: | Size: 191488 | Author: Eric | Hits:

[Other] A-compact-AES-core-with-on-line-error-detection-f

Description: This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead.
Platform: | Size: 940032 | Author: ANU MOHAN | Hits:

[Other] ALTERA

Description: we are in this file about altera fpga xilinx communication syaterm toolbox for design and system requirements
Platform: | Size: 324608 | Author: ghorbanii | Hits:
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